1. Field of Invention
The present invention relates to a memory structure and a fabricating method thereof, and more generally to a memory structure having a vertical channel and a fabricating method thereof.
2. Description of Related Art
A memory is a semiconductor device designed for storing information or data. As the functions of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. Consequently, the demand for high storage capacity memories is getting more. Among various types of memory products, a non-volatile memory such as an electrically erasable programmable read only memory (EEPROM) allows multiple-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power of the memory is interrupted. With these advantages, EEPROM has become one of the most widely adopted memories for personal computers and electronic equipment.
In a typical EEPROM, a floating gate and a control gate are made of doped polysilicon. When the memory is programmed, the electrons injected into the floating gate uniformly distributes in the polysilicon floating gate. However, when defects exist in the tunnel oxide layer under the polysilicon floating gate, a leakage current is easily generated in the device, and the reliability of the device is decreased.
In order to solve the leakage problem of the EEPROM, one known method is to adopt a charge trapping layer including a non-conductive material instead of the polysilicon floating gate. Another advantage obtained from replacing the polysilicon floating gate with the charge trapping layer is that the electrons are only stored in a portion of the charge trapping layer adjacent to the source region or drain region while the device is programmed. Therefore, during the programming process, the voltages can be applied to the source region and the control gate respectively. Hence, the electrons are stored in a portion of the charge trapping layer near the source region with a form of Gaussian distribution. Alternatively, the voltages can be applied to the drain region and the control gate respectively. Hence, the electrons are stored in a portion of the charge trapping layer near the drain region with a form of Gaussian distribution. In the other words, there are two storage regions in the charge trapping layer. Consequently, by changing the voltage applied in the control gate and the source/drain regions at the two sides thereof, two groups of electrons with Gaussian distribution, one group of electrons with Gaussian distribution, or no electrons can be present in a single charge trapping layer. Accordingly, the flash memory replacing the floating gate with the charge trapping layer can be written into a single memory cell in four states and is a flash memory with a 2 bits/cell storage.
However, the dimension of a non-volatile memory is scaled down as the degree of integration of a semiconductor device is increased. When the channel length is shortened, a punch through leakage current easily occurs between the source and drain regions, thereby lowering the performance of the memory device. In addition, as the source and drain regions are scaled down, the secondary hot electrons produced from the programming of the selected memory can not be blocked by the source and drain regions, and thus, the secondary hot electrons would inject into the adjacent memory cells. As a result, program disturbance is generated, and the reliability of the memory device is reduced.